AT89C51RB2/RC2
Bit Number
Bit Mnemonic
Description
SPR2 SPR1
SPR0 Serial Peripheral Rate
SPR1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FCLK PERIPH /2
CLK PERIPH /4
1
F
FCLK PERIPH /8
FCLK PERIPH /16
FCLK PERIPH /32
FCLK PERIPH /64
FCLK PERIPH /128
Invalid
0
SPR0
Reset Value = 0001 0100b
Not bit addressable
Serial Peripheral Status Register The Serial Peripheral Status Register contains flags to signal the following conditions:
(SPSTA)
•
•
•
Data transfer complete
Write collision
Inconsistent logic level on SS pin (mode fault error)
Table 57 describes the SPSTA register and explains the use of every bit in the register.
Table 57. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
7
6
5
4
3
-
2
-
1
-
0
-
SPIF
WCOL
SSERR
MODF
Bit
Bit
Number
Mnemonic Description
Serial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
7
SPIF
Set by hardware to indicate that the data transfer has been completed.
Write Collision Flag
Cleared by hardware to indicate that no collision has occurred or has been
approved by a clearing sequence.
6
5
4
WCOL
Set by hardware to indicate that a collision has been detected.
Synchronous Serial Slave Error Flag
SSERR Set by hardware when SS is deasserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approved by a clearing sequence.
MODF
Set by hardware to indicate that the SS pin is at inappropriate logic level.
Reserved
3
2
-
The value read from this bit is indeterminate. Do not set this bit
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
75
4180E–8051–10/06
ATMEL [ ATMEL ]
