Reset Recommendation
to Prevent Flash
Corruption
An example of bad initialization situation may occur in an instance where the bit
ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since
this bit allows mapping of the bootloader in the code area, a reset failure can be critical.
If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet
due to a bad reset) the bit ENBOOT in SFRs may be set. If the value of Program
Counter is accidently in the range of the boot memory addresses then a Flash access
(write or erase) may corrupt the Flash on-chip memory.
It is recommended to use an external reset circuitry featuring power supply monitoring to
prevent system malfunction during periods of insufficient power supply voltage (power
supply failure, power supply switched off).
Idle Mode
An instruction that sets PCON.0 indicates that it is the last instruction to be executed
before going into Idle mode. In Idle mode, the internal clock signal is gated off to the
CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is pre-
served in its entirety: the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during idle. The port pins hold the
logical states they had at the time Idle was activated. ALE and PSEN hold at logic high
level.
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will
cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will
be serviced, and following RETI the next instruction to be executed will be the one fol-
lowing the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred dur-
ing normal operation or during idle. For example, an instruction that activates idle can
also set one or both flag bits. When idle is terminated by an interrupt, the interrupt ser-
vice routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode
To save maximum power, a Power-down mode can be invoked by software (see Table
14, PCON register).
In Power-down mode, the oscillator is stopped and the instruction that invoked Power-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the Power-down mode is terminated. VCC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from Power-
down. To properly terminate Power-down, the reset or external interrupt should not be
executed before VCC is restored to its normal operating level and must be held active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0, INT1 and Keyboard Interrupts are useful to exit from
Power-down. For that, interrupt must be enabled and configured as level or edge sensi-
tive interrupt input. When Keyboard Interrupt occurs after a power down mode, 1024
clocks are necessary to exit to power down mode and enter in operating mode.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as
detailed in Figure 34. When both interrupts are enabled, the oscillator restarts as soon
as one of the two inputs is held low and power down exit will be completed when the first
input will be released. In this case, the higher priority interrupt service routine is exe-
cuted. Once the interrupt is serviced, the next instruction to be executed after RETI will
82
AT89C51RB2/RC2
4180C–8051–12/03
ATMEL [ ATMEL ]
