AT89C51RB2/RC2
Functional Block
Diagram
Figure 4. Functional Oscillator Block Diagram
Reload
Reset
CKRL
FOSC
Xtal1
Osc
1
0
8-bit
Prescaler-Divider
Xtal2
:2
1
0
CLK
X2
Peripheral Clock
PERIPH
CKCON0
CLK
CPU clock
CPU
Idle
CKRL = 0xFF?
Prescaler Divider
•
•
A hardware RESET puts the prescaler divider in the following state:
CKRL = FFh: FCLK CPU = FCLK PERIPH = FOSC/2 (Standard C51 feature)
•
Any value between FFh down to 00h can be written by software into CKRL register
in order to divide frequency of the selected oscillator:
•
CKRL = 00h: minimum frequency
F
F
CLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode)
CLK CPU = FCLK PERIPH = FOSC/510 (X2 Mode)
•
CKRL = FFh: maximum frequency
FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)
F
CLK CPU = FCLK PERIPH = FOSC (X2 Mode)
FCLK CPU and FCLK PERIPH
In X2 Mode, for CKRL<>0xFF:
FOSC
FCPU = FCLKPERIPH = -----------------------------------------------
2 × (255 CKRL)
In X1 Mode, for CKRL<>0xFF then:
FOSC
FCPU = FCLKPERIPH = -----------------------------------------------
4 × (255 CKRL)
15
4180C–8051–12/03
ATMEL [ ATMEL ]
