External Data Memory Read Cycle
TWHLH
TLLDV
ALE
PSEN
RD
TLLWL
TRLRH
TRHDZ
TAVDV
TLLAX
TRHDX
DATA IN
PORT 0
A0-A7
TRLAZ
TAVWL
ADDRESS
OR SFR-P2
PORT 2
ADDRESS A8-A15 OR SFR P2
Serial Port Timing - Shift
Register Mode
Table 80. Symbol Description
Symbol
TXLXL
Parameter
Serial port clock cycle time
TQVHX
TXHQX
TXHDX
TXHDV
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
Table 81. AC Parameters for a Fix Clock
-M
-L
Symbol
TXLXL
Min
300
200
30
Max
Min
300
200
30
Max
Units
ns
TQVHX
TXHQX
TXHDX
TXHDV
ns
ns
0
0
ns
117
117
ns
Table 82. AC Parameters for a Variable Clock
Standard
Clock
X Parameter for - X Parameter for -L
Symbol
TXLXL
Type
Min
Min
X2 Clock
6 T
M Range
Range
Units
12 T
10 T - x
2 T - x
x
ns
ns
ns
ns
ns
TQVHX
TXHQX
TXHDX
TXHDV
5 T - x
T - x
50
20
0
50
20
0
Min
Min
x
Max
10 T - x
5 T- x
133
133
116
AT89C51RB2/RC2
4180C–8051–12/03
ATMEL [ ATMEL ]
