PCA Registers
Table 53. CMOD Register
CMOD (S:D9h)
PCA Counter Mode Register
7
6
5
4
3
2
1
0
CIDL
-
-
-
-
CPS1
CPS0
ECF
Bit
Mnemonic Description
Bit Number
PCA Counter Idle Control bit
7
CIDL
Clear to let the PCA run during Idle mode.
Set to stop the PCA when Idle mode is invoked.
Reserved
6
5
4
3
-
-
-
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
EWC Count Pulse Select bits
CPS1 CPS0 Clock source
0
0
1
1
0
1
0
1
Internal Clock, FPca/6
Internal Clock, FPca/2
Timer 0 overflow
External clock at ECI/P1.2 pin (Max. Rate = FPca/4)
2-1
CPS1:0
Enable PCA Counter Overflow Interrupt bit
0
ECF
Clear to disable CF bit in CCON register to generate an interrupt.
Set to enable CF bit in CCON register to generate an interrupt.
Reset Value = 0XXX X000b
78
AT89C5115
4128F–8051–05/06
ATMEL [ ATMEL ]
