AT89C5115
Figure 17. Reading Procedure
Flash Spaces Reading
Flash Spaces Mapping
FCON = 00000aa0b
Data Read
DPTR = Address
ACC= 0
Exec: MOVC A, @A+DPTR
Clear Mode
FCON = 00h
Note:
aa = 10 for the Hardware Security Byte.
Flash Protection from Parallel The three lock bits in Hardware Security Byte (See ’In-System Programming’ section)
Programming
are programmed according to Table 23 provide different level of protection for the on-
chip code and data located in FM0 and FM1.
The only way to write this bits are the parallel mode. They are set by default to level 3.
Table 23. Program Lock bit
Program Lock bits
Security
Level
LB0
LB1
LB2
Protection Description
1
2
U
P
U
U
U
U
No program lock features enabled.
Parallel programming of the Flash is disabled.
Same as 2, also verify through parallel programming interface is
disabled. This is the factory defaul programming.
3
4
U
U
P
U
U
P
Same as 3
Note:
1. Program Lock bits
U: unprogrammed
P: programmed
WARNING: Security level 2, 3 and 4 should only be programmed after Flash and Core
verification.
Preventing Flash Corruption
See Section “Power Management”.
39
4128F–8051–05/06
ATMEL [ ATMEL ]
