AT85C51SND3Bx
USB Controller
The AT85C51SND3Bx Implements a USB controller allowing the AT85C51SND3Bx to
act as a USB device or a USB host.
The main features of the USB controller:
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Full-speed and high-speed device.
Full-speed host with OTG compliance.
Automatic Data Flow Controller (DFC) transfer without CPU support.
2368 bytes of DPRAM.
Up to 7 endpoints/pipes
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1 endpoint of 64 bytes (default control),
2 endpoints of 512 bytes max, (one or two banks),
4 endpoints of 64 bytes max, (one or two banks).
Description
The C51 core interfaces with the USB Controller using a set of special function registers
detailed in Table 49, page 39.
As shown in Figure 49, the USB controller is based on seven functional blocks:
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the PLL clock (see Section “Clock Generator”, page 28) which delivers 480 MHz
clock for USB high-speed mode support.
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the USB HS/FS pad supporting speed negotiation, attach/detach and data transfer
the USB OTG pad supporting OTG negotiation
the device controller allowing AT85C51SND3B to act as a device
the host controller allowing AT85C51SND3B to act as a device
the 2368-byte dual port RAM for endpoints and pipes memory
the interrupt controller
Figure 49. USB Controller Block Diagram
Device Controller
PLL
CLOCK
UVCC
UVCON
UID
OTG
USB Pad
CPU
Interrupt
Controller
Bus
2368 Bytes
DPRAM
DMF
DPF
DFC
Bus
Full Speed
High Speed
USB Pad
DMH
DPH
USB
Interrupt
Request
Host Controller
UBIAS
USB Connection
Figure 50 shows the connection of the AT85C51SND3B to the USB connector and the
the connection of the RC filter to the UBIAS pin. DPF and DMF pins are connected
through 2 termination resistors.
Value of all discrete components is detailed in the Section “DC Characteristics”,
page 241.
85
7632A–MP3–03/06
ATMEL [ ATMEL ]
