AT85C51SND3Bx
Clock Controller
The AT85C51SND3Bx clock controller is based on an on-chip oscillator feeding two on-
chip Phase Lock Loop (PLL) dedicated for the USB controller (see Section “USB Con-
troller”, page 85) and the Audio Controller (see Section “Audio Controller”, page 149).
All internal clocks to the peripherals and CPU core are generated by this controller.
Oscillator
X1 and X2 pins of AT85C51SND3Bx are the input and the output of a frequency power-
optimized single-stage on-chip inverter (see Figure 15) that can be configured with off-
chip components such as a Pierce oscillator (see Figure 16). Value of capacitors and
crystal characteristics are detailed in the Section “DC Characteristics”, page 241.
Authorized frequency
Power Optimization
In order to be able to be able to properly detect the oscillating frequency when in In Sys-
tem Programming mode and then generate the 480MHz requested for USB connection,
only the following frequencies are authorized:
12MHz, 13MHz, 16MHz, 19.2MHz, 19.5MHz, 20MHz, 24MHz and 26MHz.
In order to optimize the power consumption, oscillator gain can be adjusted by software
depending on the crystal frequency. Such optimization is done after reset using
OSCF1:0 bits in CKCON register (see Table 31) according to Table 23. Moreover if
external frequency signal is input (X1 driven by a remote host) it is possible to switch off
the internal amplifier by setting the OSCAMP bit in CKCON register as shown in
Figure 15.
Table 23. Oscillator Frequency Configuration
OSCF1:0
Crystal Clock Frequency Range (FOSC)
00
01
10
11
22 - 26 MHz (default)
18 - 22 MHz
14 - 18 MHz.
10 - 14 MHz
The oscillator outputs a clock: the oscillator clock used to feed the clock generator and
the system clock generator.
The oscillator clock can be disabled by entering the power-down reduction mode as
detailed in the Section “Power Management”, page 18.
Figure 15. Oscillator Block Diagram and Symbol
Oscillator
Clock
X1
CKCON4:3
OSCF1:0
OSC
CLOCK
X2
Oscillator Clock Symbol
OSCAMP
CKCON.5
PD
PCON.1
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