Figure 109. Baud Rate Generator Block Diagram
To serial
Receiver &
Transmitter
Integer
Fractional
SIO
CLOCK
÷ C
A ÷ B
Pre-Divider
Post-Divider
CDIV7:0
SBRG0
ADIV7:0
SBRG1
BDIV7:0
SBRG2
SBRG
CLOCK
Table 240. Baud Rate Generator Value (12x oversampling)
FSIO = 12 MHz
FSIO = 16 MHz
FSIO = 20 MHz
FSIO = 24 MHz
FSIO = 120 MHz(1)
Baud
Rate
A
B
C ε %
A
B
C ε %
A
B
C ε %
A
B
3
6
C ε %
A
B
C ε %
9600 125
6
5
5
5
5
5
2
1
1
1
-
0
0
0
0
0
110 99 125
0
0
0
0
0
0
124
5
7
7
7
7
7
5
1
1
1
1
-
0.007 125
5
5
5
5
5
5
2
1
1
1
1
-
0
0
0
0
0
0
110 15 142 0.033
110 49 232 0.004
110 49 116 0.004
19200 125 12
38400 125 24
57600 125 36
115200 125 72
230400 115 53
460800 115 53
921600 115 106
125
9
5
5
5
5
5
2
1
1
-
124 10
124 20
124 30
124 60
120 83
0.007 125
125 18
125 27
125 54
0.007 125 12
0.007 125 18
0.007 125 36
0.067 125 72
0.111 115 53
0.111 115 53
124
124 10
217
5
7
7
1
1
8
1
1
1
1
1
0.007
0.007
0.007
0.007
0.002
0
0.016 125 108
0.016 120 83
0.016 120 83
5
0.067 112 31
0.067 112 62
0.016 217 10
0.016 118 87
1M
1.5M
2M
1
-
1
-
0
-
112 84
0
-
115 69
110 99
0
0
-
110 55
112 84
0
0
0
-
120 12
120 18
115 23
115 46
115 92
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
-
-
-
-
1
-
1
-
0
4M
-
-
-
-
-
-
-
-
0
8M
-
-
-
-
-
-
-
-
-
-
-
-
0
Note:
1. This high frequency available through the clock generator requires PLL usage. It is
recommended to use it only for high baud rate that can not be achieved using oscilla-
tor frequency.
216
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
