AT85C51SND3Bx
Registers
Table 231. PSICON Register
PSICON (1.ADh) – PSI Control Register
7
6
5
4
3
2
1
0
PSEN
PSBSYE
PSRUNE
PSWS2
PSWS1
PSWS0
-
-
Bit
Bit
Number
Mnemonic Description
Interface Enable Bit
7
6
5
PSEN
Set to enable the PSI controller.
Clear to disable the PSI controller.
Busy Interrupt Enable Bit
PSBSYE
PSRUNE
Set to enable the busy interrupt.
Clear to disable the busy interrupt.
Overrun/Underrun Interrupt Enable Bit
Set to enable the overrun interrupt.
Clear to disable the overrun interrupt.
Write Sampling Bits
4-2
1-0
PSWS2:0
-
Data write sampling wait states after WR signal assertion from 1 clock up to 7
clock periods
Reserved
The value read from these bits is always 0. Do not set these bits.
Reset Value = 0000 0000b
Table 232. PSISTA Register
PSISTA (1.AEh) – PSI Status Register
7
6
5
4
3
2
1
0
PSEMPTY
PSBSY
PSOVR
PSRDY
-
-
-
-
Bit
Bit
Number
Mnemonic Description
FIFO Empty Flag
Set by hardware when the FIFO is empty.
Cleared by hardware when at least one data byte is present in the FIFO.
7
6
PSEMPTY
PSBSY
Busy Flag
Set by hardware when the FIFO becomes not empty (host has sent data with
SA0 = H).
Can be set or cleared by software.
Overrun/Underrun Flag
Overrun
Set by hardware when the host sends a data and the FIFO is full.
Clear by software to acknowledge the overrun condition.
5
4
PSRUN
PSRDY
Underrun
Set by hardware when the host reads a data and the FIFO is empty.
Clear by software to acknowledge the underrun condition.
Ready Flag
Set by hardware when a data is ready to be sent to the host.
Cleared by hardware at the end of a host read cycle.
211
7632A–MP3–03/06
ATMEL [ ATMEL ]
