Bit
Bit
Number
Mnemonic Description
End Of Response Interrupt Mask Bit
6
5
4
3
2
EORM
EOCM
EOFM
WFRM
HFRM
Set to prevent EORI flag from generating an interrupt.
Clear to allow EORI flag to generate an interrupt.
End Of Command Interrupt Mask Bit
Set to prevent EOCI flag from generating an interrupt.
Clear to allow EOCI flag to generate an interrupt.
End Of Frame Interrupt Mask Bit
Set to prevent EOFI flag from generating an interrupt.
Clear to allow EOFI flag to generate an interrupt.
Whole FIFO Ready Interrupt Mask Bit
Set to prevent WFRI flag from generating an interrupt.
Clear to allow WFRI flag to generate an interrupt.
Half FIFO Ready Full Interrupt Mask Bit
Set to prevent HFRI flag from generating an interrupt.
Clear to allow HFRI flag to generate an interrupt.
End Of Block Interrupt Mask Bit
1
0
EOBM
-
Set to prevent EOBI flag from generating an interrupt.
Clear to allow EOBI flag to generate an interrupt.
Reserved
The value read from this bit is always 0. Do not set this bit.
Reset Value = 1111 1110b
Table 228. MMCMD Register
MMCMD (1.B7h) – MMC Command Register
7
6
5
4
3
2
1
0
MC7
MC6
MC5
MC4
MC3
MC2
MC1
MC0
Bit
Bit
Number
Mnemonic Description
MMC Command Receive Byte
Output (read) register of the response FIFO.
MMC Command Transmit Byte
7-0
MC7:0
Input (write) register of the command FIFO.
Reset Value = 1111 1111b
Table 229. MMDAT Register
MMDAT (1.B6h) – MMC Data Register
7
6
5
4
3
2
1
0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit
Bit
Number
Mnemonic Description
MMC Data Byte
7-0
MD7:0
Input (write) or output (read) register of the data FIFO.
Reset Value = 1111 1111b
206
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
