AT85C51SND3Bx
Table 226. MMINT Register
MMINT (1.BEh Read Only) – MMC Interrupt Register
7
6
5
4
3
2
1
0
-
CDETI
EORI
EOCI
EOFI
WFRI
HFRI
EOBI
Bit
Bit
Number
Mnemonic Description
Card Detection Interrupt Flag
7
6
5
4
CDETI
EORI
EOCI
EOFI
Set by hardware every time CDET bit in MMSTA is toggling.
Cleared when reading MMINT.
End of Response Interrupt Flag
Set by hardware at the end of response reception.
Cleared when reading MMINT.
End of Command Interrupt Flag
Set by hardware at the end of command transmission.
Cleared when reading MMINT.
End of Frame Interrupt Flag
Set by hardware at the end of frame (stream, single block or multi block) transfer.
Clear when reading MMINT.
Whole FIFO Ready Interrupt Flag
Set by hardware when 16 bytes can be read in receive mode or written in
transmit mode.
Cleared when reading MMINT.
3
2
WFRI
HFRI
Half FIFO Ready Interrupt Flag
Set by hardware when 8 bytes can be read in receive mode or written in transmit
mode.
Cleared when reading MMINT.
End of Block Interrupt Flag
1
0
EOBI
-
Set by hardware at the end of block (single block or multi block) transfer.
Cleared when reading MMINT.
Reserved
The value read from this bit is always 0. Do not set this bit.
Reset Value = 0000 0000b
Table 227. MMMSK Register
MMMSK (1.BFh) – MMC Interrupt Mask Register
7
6
5
4
3
2
1
0
-
MCBM
EORM
EOCM
EOFM
WFRM
HFRM
EOBM
Bit
Bit
Number
Mnemonic Description
Card Detection Interrupt Mask Bit
7
CDETM
Set to prevent CDETI flag from generating an interrupt.
Clear to allow CDETI flag to generate an interrupt.
205
7632A–MP3–03/06
ATMEL [ ATMEL ]
