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85C51SND3BX01 参数 Datasheet PDF下载

85C51SND3BX01图片预览
型号: 85C51SND3BX01
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片数字音频解码器 - 编码器与USB 2.0接口 [Single-Chip Digital Audio Decoder - Encoder with USB 2.0 Interface]
分类和应用: 解码器编码器
文件页数/大小: 263 页 / 3620 K
品牌: ATMEL [ ATMEL ]
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Bit  
Bit  
Number  
Mnemonic Description  
Block Length LSB  
Refer to Table 220 for byte description  
7-0  
BLEN7:0  
Reset Value = 0000 0000b  
Table 225. MMSTA Register  
MMSTA (1.B5h Read Only) – MMC Status Register  
7
6
5
4
3
2
1
0
SDWP  
CDET  
CBUSY  
CRC16S  
DATFS  
CRC7S  
WFRS  
HFRS  
Bit  
Bit  
Number  
Mnemonic Description  
SD Card Write Protect Bit  
7
6
5
SDWP  
CDET  
Set by hardware when the SD card socket WP switch is opened.  
Cleared by hardware when the SD card socket WP switch is closed.  
Card Detection Bit  
Set by hardware when the SD card socket presence switch is opened.  
Cleared by hardware when the SD card socket presence switch is closed.  
Card Busy Flag  
CBUSY  
Set by hardware when the card sends a busy state on the data line.  
Cleared by hardware when the card no more sends a busy state on the data line.  
CRC16 Status Bit  
Transmission mode  
Set by hardware when the token response reports a bad CRC.  
Cleared by software by setting DCR bit in MMCON2.  
Reception mode  
Set by hardware when the CRC16 received in the data block is not correct.  
Cleared by software by setting DCR bit in MMCON2.  
4
3
CRC16S  
Data Format Status Bit  
Transmission mode  
Set by hardware when the format of the token response is correct.  
Cleared by hardware when the format of the token response is not correct.  
Reception mode  
DATFS  
Set by hardware when the format of the frame is correct.  
Cleared by hardware when the format of the frame is not correct.  
CRC7 Status Bit  
Set by hardware when the CRC7 computed in the response is correct.  
Cleared by hardware when the CRC7 computed in the response is not correct.  
2
1
0
CRC7S  
WFRS  
HFRS  
This bit is not relevant when CRCDIS is set.  
Whole FIFO Ready Status Bit  
Set by hardware when 16 bytes can be read in receive mode or written in  
transmit mode.  
Cleared by hardware when FIFO is not ready.  
Half FIFO Ready Status Bit  
Set by hardware when 8 bytes can be read in receive mode or written in transmit  
mode.  
Cleared by hardware when FIFO is not ready.  
Reset Value = XX00 0000b, depends wether a card is present in the socket or not and if  
it is locked or not.  
204  
AT85C51SND3Bx  
7632A–MP3–03/06  
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