Registers
Table 221. MMCON0 Register
MMCON0 (1.B1h) – MMC Control Register 0
7
6
5
4
3
2
1
0
-
DPTRR
CRPTR
CTPTR
MBLOCK
DFMT
RFMT
CRCDIS
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
-
The value read from this bit is always 0. do not set this bit
Data Pointer Reset Bit
DPTRR
CRPTR
CTPTR
MBLOCK
DFMT
Set to reset the read and write pointer of the data FIFO.
Cleared by hardware after pointer reset is achieved.
Command Receive Pointer Reset Bit
5
4
3
2
1
0
Set to reset the read pointer of the receive command FIFO.
Cleared by hardware after pointer reset is achieved.
Command Transmit Pointer Reset Bit
Set to reset the write pointer of the transmit command FIFO.
Cleared by hardware after pointer reset is achieved.
Multi-block Enable Bit
Set to select multi-block data format.
Clear to select single block data format.
Data Format Bit
Set to select the block-oriented data format.
Clear to select the stream data format.
Response Format Bit
RFMT
Set to select the 48-bit response format.
Clear to select the 136-bit response format.
CRC7 Disable Bit
CRCDIS
Set to disable the CRC7 computation when receiving a response.
Clear to enable the CRC7 computation when receiving a response.
Reset Value = 0000 0010b
Table 222. MMCON1 Register
MMCON1 (1.B2h) – MMC Control Register 1
7
6
5
4
3
2
1
0
BLEN3
BLEN2
BLEN1
BLEN0
DATDIR
DATEN
RESPEN
CMDEN
Bit
Bit
Number
Mnemonic Description
Block Length Bits
7-4
3
BLEN11:8
DATDIR
Refer to Table 220 for bits description.
Data Direction Bit
Set to select data transfer from host to card (write mode).
Clear to select data transfer from card to host (read mode).
202
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
