AT85C51SND3Bx
Figure 96. SD Card Write Protection Input Block Diagram
IOVDD
RPU
SDLCK
SDWP
MMSTA.7
Interrupt
As shown in Figure 97, the MMC controller implements eight interrupt sources reported
in CDETI, EORI, EOCI, EOFI, WFRI, HFRI and EOBI flags in MMCINT register. These
flags are detailed in the previous sections.
All these sources are maskable separately using CDETM, EORM, EOCM, EOFM,
WFRM, HFRM and EOBM mask bits respectively in MMMSK register.
The interrupt request is generated each time an unmasked flag is set, and the global
MMC controller interrupt enable bit is set (EMMC in IEN1 register).
Reading the MMINT register automatically clears the interrupt flags (acknowledgment).
This implies that register content must be saved, and tested flag by flag to be sure not to
forget any interrupts.
Figure 97. MMC Controller Interrupt System
CDETI
MMINT.7
CDETM
MMMSK.7
EORI
MMINT.6
EORM
MMMSK.6
EOCI
MMINT.5
EOCM
MMMSK.5
EOFI
MMINT.4
MMC
Interrupt
Request
EOFM
MMMSK.4
WFRI
MMINT.3
EMMC
IEN1.5
WFRM
MMMSK.3
HFRI
MMINT.2
HFRM
MMMSK.2
EOBI
MMINT.1
EOBM
MMMSK.1
201
7632A–MP3–03/06
ATMEL [ ATMEL ]
