Table 63. Register Bank Selection
RS1
RS0
Description
0
0
1
1
0
1
0
1
Register bank 0 from 00h to 07h
Register bank 1 from 08h to 0Fh
Register bank 2 from 10h to 17h
Register bank 3 from 18h to 1Fh
The next 16 Bytes above the register banks form a block of bit-addressable memory
space. The C51 instruction set includes a wide selection of single-bit instructions, and
the 128 bits in this area can be directly addressed by these instructions. The bit
addresses in this area are 00h to 7Fh.
Figure 26. Lower 128 Bytes Internal RAM Organization
7Fh
30h
2Fh
Bit-Addressable Space
(Bit Addresses 0-7Fh)
20h
1Fh
18h
17h
0Fh
07h
4 Banks of
8 Registers
R0-R7
10h
08h
00h
Upper 128 Bytes
The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect
addressing mode. Using direct addressing mode within this address range selects the
Special Function Registers, SFRs. For information on this segment, refer to the
Section “Special Function Registers”, page 36.
XDATA Segment
The on-chip expanded RAM (XRAM) are accessible using indirect addressing mode
through MOVX instructions.
Memory Configuration
As shown in Figure 25, the 64KB addressing space of the C51 is artificially increased by
usage of logical address over a physical one. For example, the boot memory which con-
tains the bootstrap software is implemented at physical address 10000h but is starting at
logical address code 0000h which means that the bootstrap is first executed when a
system reset occurs.
To achieve such logical mapping over the physical memory, some registers have been
implemented to give the base address of the memory segments and their size:
•
•
•
•
•
MEMCBAX (see Table 65) for the code segment base address.
MEMDBAX (see Table 66) for the data segment base address.
MEMXBAX (see Table 67) for the xdata segment base address.
MEMCSX (see Table 68) for the code segment size.
MEMXSX (see Table 69) for the code segment size.
The data segment is not programmable in size as it is a fixed 256-byte segment.
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AT85C51SND3Bx
7632A–MP3–03/06