Table 32. CKEN Register
CKEN (0.B9h) – Clock Enable Register
7
6
5
4
3
2
1
0
CKGENE
PLLEN
-
PLOCK
MMCKEN
-
SIOCKEN DNFCKEN
Bit
Bit
Number
Mnemonic Description
Clock Generator Enable Bit
7
CKGENE
Set to enable the clock generator.
Clear to disable the clock generators.
PLL Enable Bit
6
5
4
PLLEN
-
Set to enable the 480 MHz PLL.
Clear to disable the 480 MHz PLL.
Reserved
The value read from this bit is always 0. Do not set this bit.
PLL Lock Flag
PLOCK
Set by hardware when the PLL is locked.
Cleared by hardware when the PLL is not locked.
MMC Controller Clock Enable Bit
3
2
1
MMCKEN
-
Set to enable the MMC controller Clock.
Clear to disable the MMC controller Clock.
Reserved
The value read from this bit is always 0. Do not set this bit.
SIO Controller Clock Enable Bit
SIOCKEN
Set to enable the SIO Clock.
Clear to disable the SIO Clock.
DF Controller / NF Controller Clock Enable Bit
0
DNFCKEN
Set to enable the DFC/NFC Clock.
Clear to disable the DFC/NFC Clock.
Reset Value = 0000 0000b
34
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
