Table 83. MP3TRE Register
MP3TRE (S:B6h) – MP3 Treble Control Register
7
-
6
-
5
4
3
2
1
0
TRE5
TRE4
TRE3
TRE2
TRE1
TRE0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 6
5-0
-
The value read from these bits is always 0. Do not set these bits.
Treble Gain Value
Refer to Table 72 for the treble control description.
TRE5:0
Reset Value = 0000 0000b
Table 84. MP3CLK Register
MP3CLK (S:EBh) – MP3 Clock Divider Register
7
-
6
-
5
-
4
3
2
1
0
MPCD4
MPCD3
MPCD2
MPCD1
MPCD0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 5
4-0
-
The value read from these bits is always 0. Do not set these bits.
MP3 Decoder Clock Divider
5-bit divider for MP3 decoder clock generation.
MPCD4:0
Reset Value = 0000 0000b
72
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
