TS68EN360
7.8
Bus Operation – DRAM Accesses AC Timing Specification
Table 7-7.
GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure
7-20 to Figure 7-24)
25.0 MHz
33.34 MHz
Unit
Number Characteristic
Min
Max
Min
Max
100
101
102
RASx Asserted to Row Address Invalid
15
20
75
11.25
15
ns
ns
ns
RASx Asserted to column Address Valid
RASx Width Asserted
56.25
RASx width Negated (Back to back Cycle) Non page mode at
WBTQ = 0
103A
103B
103C
75
55
56.25
41.25
86.25
ns
ns
ns
RASx width Negated (Back to back Cycle) Page mode at WBTQ = 0
RASx width Negated (Back to back Cycle) Non page mode at
WBTQ = 1
115
103D
104
105
105A
106
107
108
109
110
1111
111A
113
114
115
116
117
119
120
121
122
123
124
125
RASx width Negated (Back to back Cycle) Page mode at WBTQ = 1
RASx Asserted to CASx Asserted
CLKO1 Low to CASx Asserted
95
35
3
69.23
26.25
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
13
13
10
10
10
CLKO1 High to CASx Asserted (Refresh Cycle)
CLKO1 High to CASx Negated
3
2
3
2
Column Address Valid to CASx Asserted
CASx Asserted to Column Address Negated
CASx Asserted to RASx Negated
CASx Width Asserted
15
40
35
50
95
20
35
35
52.5
55
10
3
11.25
30
27
37.5
71.25
15
CASx Width Negated (Back to Back Cycles)
CASx Width Negated (Page Mode)
WE Low to CASx Asserted
27
CASx Asserted to WE Negated
27
R/W Low to CASx Asserted (Write)
CASx Asserted to R/W High (Write)
Data-Out, Parity-Out Valid to CASx Asserted
CLKO1 High to AMUX Negated
40
41.25
7.5
16
16
2
12
12
CLKO1 High to AMUX Asserted
3
2
AMUX High to RASx Asserted
15
15
15
55
0
11.25
11.25
11.25
41.25
0
RASx Asserted to AMUX Low
AMUX Low to CASx Asserted
CASx Asserted to AMUX High
RAS/CASx Negated to R/W change
35
2113B–HIREL–06/05
ATMEL [ ATMEL ]
