Figure 7-11. SRAM: Write Cycle (TRLX = 1, CSNTQ = 1, TCYC = 0)
S0
S1
S2
S3
S4
S5
CLKO1
(OUTPUT)
A31-A0
(OUTPUT)
AS
(OUTPUT)
9C
DS
(OUTPUT)
11A
9B
12A
CSx
(OUTPUT)
14C
13A
WEx
(OUTPUT)
20
17A
22
R/W
(OUTPUT)
46
47A
DSACK0
(I/O)
31A
DSACK1
(I/O)
55
25A
26
D31-D0
(OUTPUT)
23
PRTY0-PRTY3
(OUTPUT)
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
Figure 7-12. ASYNC Bus Arbitration – IDLE Bus Case
CLKO1
(OUTPUT)
A31-A0
(OUTPUT)
D31-D0
(OUTPUT)
AS
(OUTPUT)
47A
47A
BR
(INPUT)
35
37
BG
(OUTPUT)
47A
33
34
BGACK
(INPUT)
47A
BCLRO
(OUTPUT)
60
61
30
TS68EN360
2113B–HIREL–06/05