M67206H
Pin Description
Names
I0-8
Q0-8
W
Description
Inputs
Outputs
Write Enable
Read Enable
Reset
R
RS
EF
Empty Flag
FF
Full Flag
XO/HF
XI
Expansion Out/Half-Full Flag
Expansion IN
First Load/Retransmit
Power Supply
Ground
FL/RT
VCC
GND
Data In (I0 - I8)
Reset (RS)
Data inputs for 9-bit data
Reset occurs whenever the Reset (RS) input is taken to a low state. Reset returns both
internal read and write pointers to the first location. A reset is required after power-up
before a write operation can be enabled. Both the Read Enable (R) and Write Enable
(W) inputs must be in the high state during the period shown in Figure 1 (i.e. tRSS before
the rising edge of RS) and should not change until tRSR after the rising edge of RS. The
Half-Full Flag (HF) will be reset to high After Reset (RS)
Figure 1. Reset
Notes: 1. EF, FF and HF may change status during reset, but flags will be valid at tRSC
2. W and R = VIH around the rising edge of RS.
.
3
4143J–AERO–04/07
ATMEL [ ATMEL ]
