M67025E
update the data structure. Once the update is completed the data structure may be
released.
This allows the interpreting processor, to return to read the complete data structure, thus
ensuring a consistent data structure.
Truth Table
Table 1.
Non Contention Read/Write Control
Note: Inputs
(1)
CS
H
X
L
L
L
L
L
X
H
X
H
X
L
L
Note:
X
X
R/W
X
X
L
L
H
H
H
X
H
H
OE
X
X
X
X
L
L
L
H
L
L
X
X
X
X
UB
X
H
H
L
L
H
L
X
X
H
X
H
L
X
LB
X
H
L
L
H
L
L
X
X
H
X
H
X
L
SEM
H
H
H
H
H
H
H
X
L
L
L
L
L
L
IO
8
- IO
15
Hi-Z
Hi-Z
Hi-Z
DATA
IN
DATA
OUT
Hi-Z
DATA
OUT
Hi-Z
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
–
–
Outputs
I/O
0
- I/O
7
Hi-Z
Hi-Z
DATA
IN
DATA
IN
Hi-Z
DATA
OUT
DATA
OUT
Hi-Z
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
–
–
Mode
Deselected: Power Down
Deselected: Power Down
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
Read Data in Sema. Flag
Read Data in Sema. Flag
Write D
IN0
into Sema. Flag
Write D
IN0
into Sema. Flag
Not Allowed
Not Allowed
1. A
OL
- A
12
≠
A
OR
n- A
12R
Inputs
Outputs
M/S
H
H
L
L
X
X
H
L
SEM
H
H
H
H
H
H
L
L
H
Hi-Z
BUSY
Output
Signal
Input
Signal
–
–
–
Output
Signal
–
INT
–
Table 2.
Arbitration Options
Options
Busy Logic Master
CS
L
L
L
UB
X
L
X
L
X
L
X
X
LB
L
X
L
X
L
X
X
X
Busy Logic Slave
L
L
Interrupt Logic
L
Semaphore Logic
(1)
Note:
H
H
1. Inputs Signals are for Semaphore Flags set and test (Write and Read) operations.
8
4146J–AERO–06/03
ATMEL [ ATMEL CORPORATION ]
