Figure 1-1.
Logic Diagram
2.
Pin Configurations
Table 2-1.
Pin Name
CLK
IN
I/O
GND
VCC
PD
Pin Configurations (All Pinouts Top View)
Function
Clock
Logic Inputs
Bi-directional Buffers
Ground
+5V Supply
Power-down
Figure 2-1.
CLK/IN
IN
IN
IN/PD
IN
IN
IN
IN
IN
IN
IN
GND
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
Figure 2-2.
DIP/SOIC
CLK/IN
IN
IN
IN/PD
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
Figure 2-3.
PLCC/LCC
IN
IN
CLK/IN
VCC*
VCC
I/O
I/O
4
3
2
1
28
27
26
Note:
For all PLCCs (except “-5”), pins 1, 8, 15 and 22 can be left unconnected. However, if they are
connected, superior performance will be achieved
2
Atmel ATF22V10C(Q)
0735U–PLD–7/10
IN
IN
GND
GND*
IN
I/O
I/O
12
13
14
15
16
17
18
IN/PD
IN
IN
GND*
IN
IN
IN
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O
I/O
I/O
GND*
I/O
I/O
I/O
ATMEL [ ATMEL CORPORATION ]
