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5962-895618MTX 参数 Datasheet PDF下载

5962-895618MTX图片预览
型号: 5962-895618MTX
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 128KX8, 45ns, CMOS, 0.400 INCH, FP-32]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 12 页 / 246 K
品牌: ATMEL [ ATMEL CORPORATION ]
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Write Cycle 3. CS1 or CS2 Controlled.
Note:
The internal write time of the memory is defined by the overlap of CS1 Low and CS2
HIGH and W LOW. Both signals must be actived to initiate a write and either signal can
terminate a write by going in actived. The data input setup and hold timing should be ref-
erenced to the actived edge of the signal that terminates the write. Data out is high
impedance if OE = VIH.
9
M65608E
Rev. F–20-Aug-01