Preload of Registered Outputs
The registers in the AT22V10 and AT22V10L are provided
with circuitry to allow loading of each register asynchronously
with either a high or a low. This feature will simplify testing
since any state can be forced into the registers to control test
sequencing. A V
IH
level on the I/O pin will force the register
high; a V
IL
will force it low, independent of the polarity bit (C0)
setting. The preload state is entered by placing an 11.5-V to
13-V signal on pin 8 on DIPs, and pin 10 on SMPs. When the
clock pin is pulsed high, the data on the I/O pins is placed into
the ten registers.
tD
tD
tD
Level forced on
registered output pin
during preload cycle
V
IH
V
IL
Register state
after cycle
High
Low
VH
PRELOAD
tD
tD
t
DMIN
= 100 ns
CLOCK
REGISTERED
OUTPUTS
PRELOAD ENA. FORCE I/O’S PRELOAD DATA
OUTPUTS DIS. TO VIH ORVIL CLOCKED IN
OUTPUT
VOLTAGE
REMOVED
PRELOAD
DISABLED
Power Up Reset
The registers in the AT22V10 and AT22V10L are designed to
reset during power up. At a point delayed slightly from V
CC
crossing 3.8 V, all registers will be reset to the low state. The
output state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. However,
due to the asynchronous nature of reset and the uncertainty of
how V
CC
actually rises in the system, the following conditions
are required:
1) The V
CC
rise must be monotonic,
2) After reset occurs, all input and feedback setup times must be
met before driving the clock pin high, and
3) The clock must remain stable during t
PR
.
POWER
3.8 V
tPR
REGISTERED
OUTPUTS
tW
tS
CLOCK
Parameter
t
PR
Description
Power-Up
Reset Time
Min
Typ
600
Max Units
1000
ns
Pin Capacitance
(f = 1 MHz, T = 25°C)
(1)
Typ
C
IN
C
OUT
Note:
Max
8
8
Units
pF
pF
Conditions
V
IN
= 0 V
V
OUT
= 0 V
5
6
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Erasure Characteristics
The entire fuse array of an AT22V10 or AT22V10L is erased
after exposure to ultraviolet light at a wavelength of 2537 Å.
Complete erasure is assured after a minimum of 20 minutes ex-
posure using 12,000
µ
W/cm
2
intensity lamps spaced one inch
away from the chip. Minimum erase time for lamps at other in-
1-102
tensity ratings can be calculated from the minimum integrated
erasure dose of 15 W
•
sec/cm
2
. To prevent unintentional era-
sure, an opaque label is recommended to cover the clear window
on any UV erasable PLD which will be subjected to continuous
fluorescent indoor lighting or sunlight.
AT22V10/L
ATMEL [ ATMEL CORPORATION ]
