Once set, SDP will remain active unless the disable command sequence is issued. Power transi-
tions do not disable SDP and SDP will protect the AT28C010 during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not written to the device and the memory
addresses used in the sequence may be written with data in either a byte or page write opera-
tion.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device; however, for the duration of
t
WC
, read operations will effectively be polling operations.
DEVICE IDENTIFICATION:
An extra 128-bytes of EEPROM memory are available to the user
for device identification. By raising A9 to 12V
±
0.5V and using address locations 1FF80H to
1FFFFH the bytes may be written to or read from in the same manner as the regular memory
array.
OPTIONAL CHIP ERASE MODE:
The entire device can be erased using a 6-byte software
code. Please see Software Chip Erase application note for details.
DC and AC Operating Range
AT28C010-12
Operating
Temperature (Case)
V
CC
Power Supply
Mil.
-55°C - 125°C
5V
±
10%
AT28C010-15
-55°C - 125°C
5V
±
10%
AT28C010-20
-55°C - 125°C
5V
±
10%
AT28C010-25
-55°C - 125°C
5V
±
10%
Operating Modes
Mode
Read
Write
(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Notes:
CE
V
IL
V
IL
V
IH
X
X
X
1. X can be VIL or VIH.
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
WE
V
IH
V
IL
X
V
IH
X
X
High Z
I/O
D
OUT
D
IN
High Z
2. Refer to AC Programming Waveforms
DC Characteristics
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
CC
V
IL
Parameter
Input Load Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
CC
Active Current
Input Low Voltage
Condition
V
IN
= 0V to V
CC
+ 1V
V
I/O
= 0V to V
CC
CE = V
CC
- 0.3V to V
CC
+ 1V
CE = 2.0V to V
CC
+ 1V
f = 5 MHz; I
OUT
= 0 mA
Min
Max
10
10
300
3
80
0.8
Units
μA
μA
μA
mA
mA
V
4
AT28C010 Military
0010D–PEEPR–7/09