Once set, SDP will remain active unless the disable command sequence is issued. Power transi-
tions do not disable SDP and SDP will protect the AT28C010 during power-up and power-down
conditions. All command sequences must conform to the page write timing specifications. The
data in the enable and disable command sequences is not written to the device and the memory
addresses used in the sequence may be written with data in either a byte or page write opera-
tion.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device; however, for the duration of
tWC, read operations will effectively be polling operations.
DEVICE IDENTIFICATION: An extra 128-bytes of EEPROM memory are available to the user
for device identification. By raising A9 to 12V ± 0.5V and using address locations 1FF80H to
1FFFFH the bytes may be written to or read from in the same manner as the regular memory
array.
OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software
code. Please see Software Chip Erase application note for details.
DC and AC Operating Range
AT28C010-12
-55°C - 125°C
5V ± 10%
AT28C010-15
-55°C - 125°C
5V ± 10%
AT28C010-20
-55°C - 125°C
5V ± 10%
AT28C010-25
-55°C - 125°C
5V ± 10%
Operating
Temperature (Case)
Mil.
VCC Power Supply
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X (1)
X
WE
VIH
VIL
X
I/O
Read
DOUT
DIN
Write (2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
High Z
VIH
X
X
VIL
X
VIH
X
High Z
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
Units
μA
ILI
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Active Current
VIN = 0V to VCC + 1V
VI/O = 0V to VCC
ILO
10
μA
ISB1
ISB2
ICC
CE = VCC - 0.3V to VCC + 1V
CE = 2.0V to VCC + 1V
f = 5 MHz; IOUT = 0 mA
300
3
μA
mA
mA
V
80
VIL
Input Low Voltage
0.8
4
AT28C010 Military
0010D–PEEPR–7/09
ATMEL [ ATMEL ]
