F
eatures
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SPARC V8 High Performance Low-power 32-bit Architecture
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– LEON2-FT 1.0.13 compliant
– 8 Register Windows
Advanced Architecture:
– On-chip Amba Bus
– 5 Stage Pipeline
– 16 kbyte Multi-sets Data Cache
– 32 kbyte Multi-sets Instruction Cache
On-chip Peripherals:
– Memory Interface
PROM Controller
SRAM Controller
SDRAM Controller
– Timers
Two 24-bit Timers
Watchdog Timer
– Two 8-bit UARTs
– Interrupt Controller with 4 External Programmable Inputs
– 32 Parallel I/O Interface
– 33MHz PCI Interface Compliant with 2.2 PCI Specification
Integrated 32/64-bit IEEE 754 Floating-point Unit
Fault Tolerance by Design
– Full Triple Modular Redundancy (TMR)
– EDAC Protection
– Parity Protection
Debug and Test Facilities
– Debug Support Unit (DSU) for Trace and Debug
– IEEE 1149.1 JTAG Interface
– Four Hardware Watchpoints
Speed Optimized Code RAM Interface
8, 16 and 40-bit boot-PROM (Flash) Interface Possibilities
Operating range
– Voltages
3.3V +/- 0.30V for I/O
1.8V +/- 0.15V for Core
– Temperature
-55°C to 125°C
Clock: 0MHz up to 100MHz
Power consumption: 1W at 100MHz
Performance:
– 86MIPS (Dhrystone 2.1)
– 23MFLOPS (Whetstone)
Radiation Performance
– Total dose radiation capability (parametric & functional): 60Krads (Si)
– SEU error rate better than 1 E-5 error/device/day
– No Single Event Latchup below a LET threshold of 70 MeV.cm²/mg
Package MCGA 349
Mass: 9g
Development Kit Including
– AT697 Evaluation Board
– AT697 Sample
– GRMON Development Tool
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Rad-Hard 32 bit
SPARC V8
Processor
AT697E
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Rev. 4226G–AERO–05/09
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ATMEL [ ATMEL CORPORATION ]
