ATF750C(L)
21. Power-up Reset
The registers in the ATF750C(L)s are designed to reset during power-up. At a point delayed
slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how VCC actually rises in the system, the following conditions are
required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock terms or pin high, and
3. The clock pin, or signals from which clock terms are derived, must remain stable
during tPR
.
Parameter
Description
Typ
600
2.0
Max
1000
4.5
Units
ns
tPR
Power-up Reset Time
Power-up Reset Voltage
VRST
V
22. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
5
Max
8
Units
pF
Conditions
CIN
VIN = 0V
COUT
6
8
pF
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%
tested.
11
0776L–PLD–11/08
ATMEL [ ATMEL ]
