AT68166FT
Figure 7. Write Cycle 1. WE Controlled, OE High During Write
ADDRESS
CSx
E
E
WEx
OE
I/Os
Figure 8. Write Cycle 2. WE Controlled, OE Low
ADDRESS
CSx
E
WEx
E
I/Os
Figure 9. Write Cycle 3. CS Controlled
ADDRESS
CSx
E
WEx
I/Os
The internal write time of the memory is defined by the overlap of CS Low and WE LOW. Both signals must
be activated to initiate a write and either signal can terminate a write by going in active mode. The data
input setup and hold timing should be referenced to the active edge of the signal that terminates the write.
Data out is high impedance if OE= VIH.
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7531H–AERO–04/09