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5962-0622903QYC 参数 Datasheet PDF下载

5962-0622903QYC图片预览
型号: 5962-0622903QYC
PDF下载: 下载PDF文件 查看货源
内容描述: 抗辐射16兆3.3V 5V容错SRAM的多芯片模块 [Rad Hard 16 MegaBit 3.3V 5V Tolerant SRAM Multi- Chip Module]
分类和应用: 存储内存集成电路静态存储器异步传输模式ATM
文件页数/大小: 19 页 / 376 K
品牌: ATMEL [ ATMEL ]
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Consumption  
AT68166FT-25  
AT68166FT-20  
AT68166FT-18  
(preliminary)  
TAVAV/TAVAW  
Test Condition  
Symbol  
Description  
Unit  
Value  
Standby  
Supply  
Current  
(1)  
ICCSB  
10  
8
7
6
7.5  
7
mA  
max  
Standby  
Supply  
Current  
(2)  
ICCSB1  
mA  
mA  
max  
max  
18 ns  
20 ns  
25 ns  
50 ns  
1 µs  
170  
165  
145  
80  
(3)  
165  
145  
80  
ICCOP  
Dynamic  
Operating  
Current  
Read per  
byte  
150  
85  
15  
12  
12  
18 ns  
20 ns  
25 ns  
50 ns  
1 µs  
145  
140  
135  
115  
105  
(4)  
140  
135  
115  
105  
ICCOP  
Dynamic  
Operating  
Current  
Write per  
byte  
150  
125  
110  
mA  
max  
Notes: 1. All CSx >VIH  
2. All CSx > VCC - 0.3V  
3. F = 1/TAVAV, Iout = 0 mA, WEx = OE = VIH, VIN = GND/VCC, VCC max.  
4. F = 1/TAVAW, Iout = 0 mA, WEx = VIL, OE = VIH , VIN = GND/VCC, VCC max.  
Data Retention  
Mode  
Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and sup-  
ply current are guaranteed over temperature. The following rules insure data retention:  
1. During data retention chip select CSx must be held high within VCC to VCC -0.2V.  
2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, mini-  
mizing power dissipation.  
3. During power-up and power-down transitions CSx and OE must be kept between VCC  
0.3V and 70% of VCC.  
+
4. The RAM can begin operation > tR ns after VCC reaches the minimum operation voltages  
(3V).  
Figure 5. Data Retention Timing  
vcc  
CSx  
8
AT68166FT  
7531H–AERO–04/09  
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