AT60142FT
Data Retention Mode
Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage
and supply current are guaranteed over temperature. The following rules insure data
retention:
1. During data retention chip select CS must be held high within VCC to VCC -0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high imped-
ance, minimizing power dissipation.
3. During power-up and power-down transitions CS and OE must be kept between
VCC + 0.3V and 70% of VCC.
4. The RAM can begin operation > tR ns after VCC reaches the minimum operation
voltages (3V).
Figure 1. Data Retention Timing
Data Retention Characteristics
Parameter
Description
Min
Typ TA = 25°C
Max
Unit
VCCDR
VCC for data retention
2.0
–
–
V
Chip deselect to data
retention time
tCDR
0.0
–
–
–
–
ns
ns
Operation recovery
time
(1)
tR
tAVAV
1.5 (AT60142FT-15)
1.3 (AT60142FT-17)
(2)
ICCDR
Data retention current
–
0.700
mA
1.
2.
TAVAV = Read cycle time.
CS = VCC, VIN = GND/VCC
.
6
7726B–AERO–04/09
ATMEL [ ATMEL ]
