data flows through the bit. When a nibble is not (Write) addressed or LOAD is logic 0 or
WE is logic 1, data is latched in the nibble. The two CLOCK muxes are controlled
together; they both select CLOCK (for a synchronous RAM) or they both select “1” (for
an asynchronous RAM). CLOCK is obtained from the clock for the sector-column imme-
diately to the left and immediately above the RAM block. Writing any value to the RAM
clear byte during configuration clears the RAM (see the “AT40K/40KAL Configuration
Series” application note at www.atmel.com).
Figure 8. RAM Logic
CLOCK
“1”
“1”
0
1
1
0
Load
5
Read Address
Write Address
Ain
Load
Latch
5
Aout
32 x 4
Dual-port
RAM
“1”
OE
Load
Latch
WEN
Write Enable NOT
Load
Latch
4
4
Din
Din
Dout
Dout
Clear
RAM-Clear Byte
Figure 9 on page 13 shows an example of a RAM macro constructed using
AT40KEL040’s FreeRAM cells. The macro shown is a 128 x 8 dual-ported asynchro-
nous RAM. Note the very small amount of external logic required to complete the
address decoding for the macro. Most of the logic cells (core cells) in the sectors occu-
pied by the RAM will be unused: they can be used for other logic in the design. This
logic can be automatically generated using the macro generators.
12
AT40KEL040
4155I–AERO–06/06
ATMEL [ ATMEL ]
