29C516E
Table 8:
Function
1
0
x
1
1
0
UD1[0..15] = MD[0..15]
1
1
1
1
0
0
0
0
x
x
x
x
x
x
UD1[0..15] = {corrected MD[0..15]}
UD1[0..15] = {corrupted MD[0..15]}
UD1[0..15] = MD[0..15]
0
x
1
0
1
0
x
x
x
x
UD1[0..15] = {MC[0..7] Syndrome}
UD1[0..15] = H.Z
1
x
x
x
1
x
1
1
x
1
x
0
x
0
x
1
x
1
x
1
0
x
x
1
1
0
UD2[0..15] = {expected UD1[0..15]} (User 2 listening)
UD2[0..15] = MD[0..15]
x
x
x
x
x
x
1
1
0
0
UD2[0..15] = {corrected MD[0..15]}
UD2[0..15] = {corrupted MD[0..15]}
UD2[0..15] = MD[0..15]
0
x
1
0
1
1
0
0
x
x
x
UD2[0..15] = {MC[0..7] Syndrome}
UD2[0..15] = H.Z
1
x
x
x
1
x
x
1
x
0
x
0
1
1
x
x
x
x
x
UD1[0..15] = {expected UD2[0..15]} (User 1 listening)
x : don’t care
9.2. Memory Write
The TRANS pin is driven at a high level to select the MEMx and ENx. All transaction managed by the master
access to the memory. The external arbiter drives the user can be listened by the second user.
U2/U1 pin and dispatches the commands RD/WRx,
Table 9:
Function
MD[0..15] = UD1[0..15]
MC[0..7] = {check–bits generated from UD1[0..15]}
0
0
0
0
x
x
x
x
x
x
1
x
x
x
1
x
MD[0..15] = H.Z
1
1
0
1
MC[0..7] = H.Z
0
x
1
0
0
0
0
0
UD2[0..15] = UD1[0..15] (User 2 listening)
MD[0..15] = UD2[0..15]
MC[0..7] = {check–bits generated from UD2[0..15]}
x
x
1
x
x
x
1
x
MD[0..15] = H.Z
x
1
x
0
x
0
0
0
MC[0..7] = H.Z
UD1[0..15] = UD2[0..15] (User 1 listening)
x : don’t care
CERR and NCERR are not valid
CORRECT and SYNCHK are not active
10
Rev. E (03 2007)
ATMEL [ ATMEL ]
