29C516E
3.4. Pin Description
Table 1:
Name
Pin Description
I/O
Active
Description
Buses
U1D[0..15]
U2D[0..15]
ΜD[0..15]
ΜC[0..7]
Error Flags
CERR
NCERR
26
25
O
O
Low
Low
Correctable Error
Uncorrectable Error
53,49..47,45..42,40..37,35..33,28
23..20,18..15,13..10,8..5
59..62,64..67,69..72,74..77
83..86,88..91
I/O*
I/O*
I/O*
I/O*
High
High
High
High
User 1 Data Bus
User 2 Data Bus
Memory Data Bus
Memory Check–bit Bus
General Control Signals
CORRECT
SYNCHK
N22
TRANS
98
97
27
96
I*
I*
I*
I*
High
Low
High
H/L
When active, the EDAC is in CORRECT mode. If low,
the EDAC is in DETECT mode.
Selects the Syndrome bits (high byte) and the Check–bits
(low byte) to be driven on the selected User Data Bus.
When active, the EDAC uses 6 check–bits. If low, the
EDAC uses 8 check–bits in memory read.
Selects the Data path to be used. If high, the EDAC
access the memory, if low, the EDAC access the transfer
buffer.
Selects who is the master of User 1 and User 2. The
master is responsible for applying RD/WRx, MEMx, and
ENx signals in a correct way.
U2/U1
95
I*
H/L
User 1 Control Signals
RD/WRT
EN1
MEM1
55
56
57
I*
I*
I*
H/L
Low
Low
User 1 Read/Write signal
User 1 Output Enable
User 1 Memory Select
User 1 Control Signals
RD/WR2
EN2
MEM2
Power (Buffers)
VCC
B
GND
B
Power (Core)
VCC
C
GND
C
100
93
I
I
–
–
Core supply (5 V nominal)
Core 0 V reference
9,19,32,41,54,63,73,87
4,14,24,36,46,58,68,78,92
I
I
–
–
Buffers supply (5 V nominal)
Buffers 0 V nominal reference
99
94
3
I*
I*
I*
H/L
Low
Low
User 2 Read/Write signal
User 2 Output Enable
User 2 Memory Select
* Pull–up buffers
4
Rev.
E
(03
2007)
ATMEL [ ATMEL CORPORATION ]
