Block Diagram
Figure 1.
TSC695F Block Diagram
TAP
32-bit
Integer
Unit
DMA
Arbiter
Access
Controller
Wait State
Controller
Address
Interface
EDAC
General Purpose
Interface
UART B
UART A
Interrupt
Controller
Parity
Gen./Check.
DMA Ctrl
Clock
&
Parity
Reset
Gen./Chk.
Managt
32/64-bit
Floating-Point
Unit
Parity
Gen./Chk.
Mem Ctrl
Ready/Busy
Add.+Size+ASI
Error
Managt
General Purpose
Timer
Real Time Clock
Timer
Watch
Dog
Data+Check bits
Parities
GPI bits
RxD, TxD
Interrupts
Pin Descriptions
Table 1.
Pin Descriptions
Signal
RA[31:0]
RAPAR
RASI[3:0]
RSIZE[1:0]
RASPAR
CPAR
D[31:0]
CB[6:0]
DPAR
RLDSTO
ALE
DXFER
LOCK
RD
WE
WRT
MHOLD
MDS
MEXC
PROM8
BA[1:0]
ROMCS
ROMWRT
MEMCS[9:0]
MEMWR
Type
I/O,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
O
O
I
O
O
For pin assignment, refer to package section.
Active
Description
32-bit registered address bus
Output buffer: 400 pF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHOLD+FHOLD
+BHOLD+FCCV
-
-
-
-
-
-
Output buffer: 400 pF
Output buffer: 400 pF
High
Registered address bus parity
4-bit registered address space identifier
2-bit registered bus transaction size
High
High
Registered ASI and SIZE parity
Control bus parity
32-bit data bus
7-bit check-bit bus
High
High
Low
High
High
High
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
Data bus parity
Registered atomic load-store
Address latch enable
Data transfer
Bus lock
Read access
Write enable
Advanced write
Memory bus hold
Memory data strobe
Memory exception
Select 8-bit wide PROM
Latched address used for 8-bit wide boot PROM
PROM chip select
ROM write enable
Memory chip select
Memory write strobe
2
TSC695F
4118H–AERO–06/03
ATMEL [ ATMEL CORPORATION ]
