1 (RAM fetch)
2 (RAM atomic load store)
3 (RAM fetch)
t4_1
t2
SYSCLK
RA [31:0]
t4_1
FA1
ALSA
FA5
ALE*
t5
t5
t5
t5
MEMCS* [0]
MEMCS* [1]
t6
t6
t6
t6
DDIR
t7
t7
MEMWR*
BUFFEN*
t8
t56
t8
t56
t8
OE*
t10
t10
t61
t9
t9
t11
t11
t12
FD1
FP1
FC1
FD5
FP5
FC5
D [31:0]
DPAR
byte from RAM
word from RAM
t10
word to RAM
t10
t9
t61
t9
t12
t12
parity from RAM
t10
parity to RAM
parity from RAM
t10
t9
t61
t9
t13
checkbyte to RAM
CB [6:0]
INST
checkbyte from RAM
checkbyte from RAM
t60
t60
t16
t16
held to update the full word
MHOLD*
MDS*
t46
t46
INULL
RLDSTO
LOCK
t4_1
t4_1
t4_2
t4_2