Pin Description
MNEMONIC
VSS
Type
Name and Function
I
Ground: 0V reference
Power Supply: This is the power supply voltage for normal, idle and power-down
operation
VCC
I
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 pins must
be polarized to Vcc or Vss in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal pull-
up when emitting 1s.
P0.0-P0.7
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally pulled low will source current
because of the internal pull-ups.
P1.0-P1.7
P2.0-P2.7
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current
because of the internal pull-ups. Port 2 emits the high-order address byte during
fetches from external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses
strong internal pull-ups emitting 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
I/O
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the internal pull-ups. Port 3 also serves the special features of the
80C51 family, as listed below.
I
O
I
RXD (P3.0): Serial input port
TXD (P3.1): Serial output port
P3.0-P3.7
INT0 (P3.2): External interrupt 0
INT1 (P3.3): External interrupt 1
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
I
I
I
O
O
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power-on reset
using only an external capacitor to VCC.
RST
ALE
I
Address Latch Enable: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a
O (I) constant rate of 1/6 the oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each access to external data
memory.
Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
PSEN
O
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
4
80C32E
Rev. K – 21-Aug-01
ATMEL [ ATMEL ]
