欢迎访问ic37.com |
会员登录 免费注册
发布采购

49F010 参数 Datasheet PDF下载

49F010图片预览
型号: 49F010
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位128K ×8 5伏只有CMOS闪存 [1-Megabit 128K x 8 5-volt Only CMOS Flash Memory]
分类和应用: 闪存
文件页数/大小: 10 页 / 251 K
品牌: ATMEL [ ATMEL CORPORATION ]
 浏览型号49F010的Datasheet PDF文件第1页浏览型号49F010的Datasheet PDF文件第2页浏览型号49F010的Datasheet PDF文件第4页浏览型号49F010的Datasheet PDF文件第5页浏览型号49F010的Datasheet PDF文件第6页浏览型号49F010的Datasheet PDF文件第7页浏览型号49F010的Datasheet PDF文件第8页浏览型号49F010的Datasheet PDF文件第9页  
AT49F010/HF010
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING:
The AT49F010/HF010 features DATA
polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA
polling may begin at any time during the program cycle.
T O G G L E B I T :
I n a d d i t i o n t o DATA p o l l i n g t h e
AT49F010/HF010 provides another method for determin-
ing the end of a program or erase cycle. During a program
or erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the
AT49F010/HF010 in the following ways: (a) V
CC
sense: if
V
CC
is below 3.8V (typical), the program function is inhib-
ited. (b) Program inhibit: holding any one of OE low, CE
high or WE high inhibits program cycles. (c) Noise filter:
Pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
Command Definition (in Hex)
Command
Bus
Sequence
Cycles
Read
Chip Erase
Byte
Program
Boot Block
(1)
Lockout
Product ID
Entry
Product ID
(2)
Exit
Product ID
(2)
Exit
1
6
4
6
3
3
1
1st Bus
Cycle
Addr
Addr
5555
5555
5555
5555
5555
XXXX
Data
D
OUT
AA
AA
AA
AA
AA
F0
2nd Bus
Cycle
Addr
2AAA
2AAA
2AAA
2AAA
2AAA
Data
55
55
55
55
55
3rd Bus
Cycle
Addr
5555
5555
5555
5555
5555
Data
80
A0
80
90
F0
4th Bus
Cycle
Addr
5555
Addr
5555
Data
AA
D
IN
AA
5th Bus
Cycle
Addr
2AAA
Data
55
6th Bus
Cycle
Addr
5555
Data
10
2AAA
55
5555
40
Notes: 1. The 8K byte boot sector has the address range 00000H to 01FFFH.
2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
3