4.1.5
ITC Mode
Principle: An external sync controls both the integration time and the frame rate.
The trigger event initiates the following sequence:
• Stop of readout frame in progress and reset of readout pointer to line 1
• Shutter output signal is activated during a time defined by the high state of the ITC signal
• Readout of frame N. The readout data is forwarded to the Camera Link interface (FVAL
active) starting with the first line
• Readout of dummy frames (to prevent against large dark current integration) while the
camera waits for the next trigger event
The integration delay is a few µs. The minimum pulse duration is 1 µs. The source of ITC signal
is selectable between Camera Link CC1 signal and TTL_IO trigger input. See Register Mode
Control @ 204H Internal Register Mapping on page 16. The period is defined by the ITC signal
period.
As the integration time is not the same for all lines (in the following timing diagram line n integra-
tion time is greater than line 1 integration time) this mode must be used with a pulsed light
source or a shutter element. Moreover any residual light when shutter output signal is inhibited
must be avoided. The exposure time is defined by the ITC signal high state time and all the lines
are exposed during the same time.
Figure 4-5. ITC Mode Chronogram
Trigger N Event
ITC in
Line 1
Trigger Delay
Integration
Line 1 Readout
and Reset
Line 1 Reset
(Frame N)
Line n
Integration
(Frame N)
Line n Readout
and Reset
Line n Reset
Frame N
Readout
Shutter out
Shutter Time
FVAL
10
ATMOS -2M60/2M30 [Preliminary]
5440A–IMAGE–10/05
ATMEL [ ATMEL ]
