AX88196
Local CPU BUS MAC Controller
CONTENTS
1.0 INTRODUCTION ...............................................................................................................................................4
1.1 GENERAL DESCRIPTION: .....................................................................................................................................4
1.2 AX88196 BLOCK DIAGRAM:...............................................................................................................................4
1.3 AX88196 PIN CONNECTION DIAGRAM ................................................................................................................5
1.3.1 AX88196 Pin Connection Diagram for ISA Bus Mode.................................................................................6
1.3.2 AX88196 Pin Connection Diagram for 80x86 Mode....................................................................................7
1.3.3 AX88196 Pin Connection Diagram for MC68K Mode.................................................................................8
1.3.4 AX88196 Pin Connection Diagram for MCS-51 Mode ................................................................................9
2.0 SIGNAL DESCRIPTION..................................................................................................................................10
2.1 LOCAL CPU BUS INTERFACE SIGNALS GROUP....................................................................................................10
2.2 MII INTERFACE SIGNALS GROUP ........................................................................................................................11
2.3 EEPROM SIGNALS GROUP ...............................................................................................................................12
2.4 SNI INTERFACE PINS GROUP..............................................................................................................................12
2.5 STANDARD PRINTER PORT INTERFACE PINS GROUP.............................................................................................12
2.6 POWER ON CONFIGURATION SETUP SIGNALS PINS GROUP .....................................................................................13
2.7 MISCELLANEOUS PINS GROUP ............................................................................................................................13
3.0 MEMORY AND I/O MAPPING ......................................................................................................................15
3.1 EEPROM MEMORY MAPPING ..........................................................................................................................15
3.2 I/O MAPPING....................................................................................................................................................15
3.3 SRAM MEMORY MAPPING ...............................................................................................................................15
4.0 REGISTERS OPERATION..............................................................................................................................16
4.1 COMMAND REGISTER (CR) OFFSET 00H (READ/WRITE) ...................................................................................18
4.2 INTERRUPT STATUS REGISTER (ISR) OFFSET 07H (READ/WRITE)......................................................................18
4.3 INTERRUPT MASK REGISTER (IMR) OFFSET 0FH (WRITE)..................................................................................19
4.4 DATA CONFIGURATION REGISTER (DCR) OFFSET 0EH (WRITE)........................................................................19
4.5 TRANSMIT CONFIGURATION REGISTER (TCR) OFFSET 0DH (WRITE).................................................................19
4.6 TRANSMIT STATUS REGISTER (TSR) OFFSET 04H (READ).................................................................................20
4.7 RECEIVE CONFIGURATION (RCR) OFFSET 0CH (WRITE)...................................................................................20
4.8 RECEIVE STATUS REGISTER (RSR) OFFSET 0CH (READ) ...................................................................................20
4.9 INTER-FRAME GAP (IFG) OFFSET 16H (READ/WRITE).......................................................................................21
4.10 INTER-FRAME GAP SEGMENT 1(IFGS1) OFFSET 12H (READ/WRITE)................................................................21
4.11 INTER-FRAME GAP SEGMENT 2(IFGS2) OFFSET 13H (READ/WRITE)................................................................21
4.12 MII/EEPROM MANAGEMENT REGISTER (MEMR) OFFSET 14H (READ/WRITE)...............................................21
4.13 TEST REGISTER (TR) OFFSET 15H (WRITE)....................................................................................................21
4.14 SPP DATA PORT REGISTER (SPP_DPR) OFFSET 18H (READ/WRITE)...............................................................22
4.15 SPP STATUS PORT REGISTER (SPP_SPR) OFFSET 19H (READ)........................................................................22
4.16 SPP COMMAND PORT REGISTER (SPP_CPR) OFFSET 1AH (READ/WRITE) ......................................................22
5.0 CPU I/O READ AND WRITE FUNCTIONS..................................................................................................23
5.1 ISA BUS TYPE ACCESS FUNCTIONS. ....................................................................................................................23
5.2 80186 CPU BUS TYPE ACCESS FUNCTIONS. ........................................................................................................23
5.3 MC68K CPU BUS TYPE ACCESS FUNCTIONS.......................................................................................................24
5.4 MCS-51 CPU BUS TYPE ACCESS FUNCTIONS......................................................................................................24
6.0 ELECTRICAL SPECIFICATION AND TIMINGS .......................................................................................25
6.1 ABSOLUTE MAXIMUM RATINGS.........................................................................................................................25
6.2 GENERAL OPERATION CONDITIONS ...................................................................................................................25
6.3 DC CHARACTERISTICS......................................................................................................................................25
6.4 A.C. TIMING CHARACTERISTICS........................................................................................................................26
6.4.1 XTAL / CLOCK.........................................................................................................................................26
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ASIX ELECTRONICS CORPORATION
ASIX [ ASIX ELECTRONICS CORPORATION ]
