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AX88196L 参数 Datasheet PDF下载

AX88196L图片预览
型号: AX88196L
PDF下载: 下载PDF文件 查看货源
内容描述: 10 / 100BASE 3合1本地CPU总线快速以太网控制器与嵌入式SRAM [10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM]
分类和应用: 静态存储器控制器以太网局域网(LAN)标准
文件页数/大小: 42 页 / 588 K
品牌: ASIX [ ASIX ELECTRONICS CORPORATION ]
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AX88196  
Local CPU BUS MAC Controller  
2.0 Signal Description  
The following terms describe the AX88196 pin-out:  
All pin names with the “/” suffix are asserted low.  
The following abbreviations are used in following Tables.  
I
O
I/O  
OD  
Input  
Output  
Input/Output  
Open Drain  
PU  
PD  
P
Pull Up  
Pull Down  
Power Pin  
2.1 Local CPU Bus Interface Signals Group  
SIGNAL  
SAL[2:0]  
TYPE  
I/PD  
PIN NO.  
DESCRIPTION  
113 – 111 System Address Select Low : Signals SAL[2:0] are additional address  
signal input lines which active low enable higher I/O address decoder  
on chip.  
SAH[2:0]  
I/PU  
116 – 114 System Address Select High : Signals SAH[2:0] are additional  
address signal input lines which active high enable higher I/O  
address decoder on chip.  
SA[9:1],  
SA[0]/UDS  
I
I
10 – 1  
System Address : Signals SA[9:0] are address bus input lines which  
lower I/O spaces on chip. SA[0] also means Upper Data Strobe  
(/UDS) active low signal in 68K application mode  
Bus High Enable or Lower Data Strobe : Bus High Enable is active  
low signal in some 16 bit application mode which enable high bus  
(SD[15:8]) active. The signal also name as Lower Data Strobe (LDS)  
for 68K application mode.  
/BHE  
or  
/LDS  
18  
SD[15:0]  
I/O  
O
20 – 23,  
25 – 28,  
30 – 33,  
35 – 38  
12  
System Data Bus : Signals SD[15:0] constitute the bi-directional data  
bus.  
IREQ/IREQ  
Interrupt Request : When ISA BUS or 80186 CPU mode is select.  
IREQ is asserted high to indicate the host system that the chip  
requires host software service. When MC68K or MCS-51 CPU mode  
is select. /IREQ is asserted low to indicate the host system that the  
chip requires host software service.  
RDY/DTACK  
OD  
125  
Ready : This signal is set low to insert wait states during Remote  
DMA transfer.  
/Dtack : When Motorola CPU type is select, the pin is active low  
inform CPU that data is accepted.  
/CS  
I
I
I
123  
15  
Chip Select  
When the /CS signal is asserted, the chip is selected.  
I/O Read :The host asserts /IORD to read data from AX88196 I/O  
space. When Motorola CPU type is select , the pin is useless.  
I/O Write :The host asserts /IOWR to write data into AX88196 I/O  
space. When Motorola CPU type is select, the pin is active high for  
read operation at the same time.  
/IORD  
/IOWR  
or  
R/W  
14  
/OCS16  
OD  
120  
I/O is 16 Bit Port : The /IOIS16 is asserted when the address at the  
range corresponds to an I/O address to which the chip responds, and  
the I/O port addressed is capable of 16-bit access.  
10  
ASIX ELECTRONICS CORPORATION