AX88178
USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller
Trclk
Trch
Trcl
RX_CLK (RXC)
RXD [3:0]
Trsu Trhd
RXD [3:0] RXD [7:4]
Trsu Trhd
RX_DV (RX_CTL)
RX_DV
RX_ER
Symbol
Description
Min Typ Max Units
Ttclk TXC clock cycle time at 1000Mbps *1
7.2 8.0 8.8
ns
ns
ns
ps
ns
ns
ns
ns
ns
Ttch TXC clock high time at 1000Mbps *2
-
-
4.0
4.0
-
-
-
Ttcl
TXC clock low time at 1000Mbps *2
T TXC clock to TXD [3:0] and TX_EN output skew (at transmitter)
TSKEW
-500
500
Trclk RX_CLK (RXC) clock cycle time at 1000Mbps *1
Trch RX_CLK (RXC) clock high time at 1000Mbps *2
Trcl RX_CLK (RXC) clock low time at 1000Mbps *2
7.2 8.0 8.8
-
-
4.0
4.0
-
-
-
-
-
Trsu RXD [3:0] and RX_DV (RX_CTL) to RX_CLK (RXC) clock setup time 1.0
Trhd RXD [3:0] and RX_DV (RX_CTL) to RX_CLK (RXC) clock hold time 1.0
-
*1: For 10Mbps and 100Mbps, Ttclk and Trclk shall scale to 400ns+/-40ns and 40ns+/-4ns respectively.
*2: For 10Mbps and 100Mbps, the typical value of Ttch, Ttcl, Trch, and Trcl shall scale to 200ns and 20ns respectively.
7.4.5 MII Timing (100Mbps)
Ttclk
Ttch Ttcl
TX_CLK
Tts
Tth
TXD [3:0]
TX_EN, TX_ER
Symbol
Description
Min
-
-
Typ
Max
Units
ns
ns
ns
ns
Ttclk TX_CLK clock cycle time *1
40.0
20.0
20.0
-
-
-
-
-
-
Ttch TX_CLK clock high time *2
Ttcl
Tts
TX_CLK clock low time *2
-
TXD [3:0], TX_EN, TX_ER setup time
TXD [3:0], TX_EN, TX_ER hold time
28.0
5.0
Tth
-
ns
31
ASIX ELECTRONICS CORPORATION
ASIX [ ASIX ELECTRONICS CORPORATION ]
