plerow
TM
ALN1765AT
Internally Matched LNA Module
Application Circuit
V
S
+
-
Tantal or MLC (Multi Layer Ceramic)
Capacitor
(Mandatory)
C1
IN
C4 = 100pF
C2
ALN
C3 = 0.5pF
(Mandatory)
OUT
1)
The tantal or MLC (Multi Layer Ceramic) capacitor is optional and for bypassing the AC noise introduced
from the DC supply. The capacitance value may be determined by customer’s DC supply status. The ca-
pacitor should be placed as close as possible to V
s
pin and be connected directly to the ground plane for
the best electrical performance.
DC blocking capacitors are always necessarily placed at the input and output port for allowing only the
RF signal to pass and blocking the DC component in the signal. The DC blocking capacitors are in-
cluded inside the ALN module. Therefore, C1 & C2 capacitors may not be necessary, but can be added
just in case that the customer wants. The value of C1 & C2 is determined by considering the application
frequency. C3 and C4 in the blue dot line circle shall be used for matching.
2)
Recommended Soldering Reflow Process
Evaluation Board Layout
Vs
260°C
Ramp-up
(3˚C/sec)
200°C
20~40 sec
Ramp-down
(6°C/sec)
IN
OUT
150°C
60~180 sec
Size 25x25mm
(for ALN-AT, BT, T Series – 10x10mm)
4/4
www.asb.co.kr
March 2009
ASB [ ADVANCED SEMICONDUCTOR BUSINESS INC. ]
