CS5490
6.6 Register Descriptions
21. “Default” = bit states after power-on or reset
22. DO NOT write a “1” to any unpublished register bit or to a bit published as “0”.
23. DO NOT write a “0” to any bit published as “1”.
24. DO NOT write to any unpublished register address.
6.6.1 Configuration 0 (Config0) – Page 0, Address 0
23
22
21
20
19
18
17
16
1
1
0
0
-
-
-
-
15
14
13
12
11
10
9
8
-
0
1
-
-
-
-
INT_POL
7
6
5
4
3
2
1
0
-
-
IPGA[1]
IPGA[0]
-
NO_OSC
0
0
Default = 0xC0 2000
[23:9]
Reserved.
INT_POL
Interrupt Polarity.
0 = Active low (Default)
1 = Active high
[7:6]
Reserved.
IPGA[1:0]
Select PGA gain for I channel.
00 = gain (Default)
10 = 50x gain
[3]
Reserved.
NO_OSC
Disable crystal oscillator (making XIN a logic-level input).
0 = Crystal oscillator enabled (Default)
1 = Crystal oscillator disabled
DS982F2
31
APEX [ CIRRUS LOGIC ]
