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APL5331G5C-TRL 参数 Datasheet PDF下载

APL5331G5C-TRL图片预览
型号: APL5331G5C-TRL
PDF下载: 下载PDF文件 查看货源
内容描述: 3A总线终端稳压器 [3A Bus Termination Regulator]
分类和应用: 稳压器
文件页数/大小: 20 页 / 231 K
品牌: ANPEC [ ANPEC ELECTRONICS COROPRATION ]
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APL5331  
plane reduces the resistance cCA . The relationship  
between power dissipation and temperatures is the  
following equation :  
A capacitor of 1µF (ceramic chip capacitor) or greater  
(aluminum electrolytic capacitor) is recommended to  
connect near VCNTL pin. For VIN pin, an aluminum  
electrolytic capacitor (>50µF) is recommended. It is  
not necessary to use low-ESR capacitors.  
PD = (TJ - TA) / cJA  
where,  
PD : Power dissipation  
TJ : Junction Temperature  
TA : Ambient Temperature  
cJA : Junction-to-Ambient Thermal Resis-  
tance  
Layout and Thermal Consideration  
The input capacitors for VIN and VCNTL pins are  
normally placed near each pin for good  
performances. Ceramic decoupling capacitors at  
output must be placed as close to the load to reduce  
the parasitic inductors of traces. It is also recom-  
mended that the APL5331 and output capacitors are  
placed near the load for good load regulation and  
load transient response. The negative pins of the in-  
put and output capacitors and the GND pin of the  
APL5331 should connect to analog ground plane of  
the load.  
102 mil  
SOP-8-P  
118 mil  
Thermal  
Top  
ground  
pad  
D ie  
See figure 1. The SOP-8-P utilizes a bottom thermal  
pad to minimize the thermal resistance of the package,  
making the package suitable for high current  
applications. The thermal pad is soldered to the top  
ground pad and is connected to the internal or bot-  
tom ground plane by several vias. The printed circuit  
board (PCB) forms a heat sink and dissipates most  
of the heat into ambient air. The vias are recom-  
mended to have proper size to retain solder, helping  
heat conduction.  
pad  
Ambient  
Air  
Vias Internal  
ground  
Printed  
circuit  
board  
plane  
Figure 1 Package Top and side view  
Figure 2 shows a board layout using the SOP-8-P  
package. The demo board is made of FR-4 material  
and is a two-layer PCB. The size and thickness are  
65mm* 65mm and 1.6mm. An area of 140mil*105mil  
on the top layer is use as a thermal pad for the  
APL5331 and this is connected to the bottom layer  
by vias. The bottom layer using 2 oz. copper acts as  
the ground plane for the system. The PCB and all  
components on the board form a heat sink. The cJA  
of the APL5331(SOP-8-P) mounted on this demo  
board is about 37oC/W in free air. Assuming the  
TA=25oC and the maximum TJ=150oC (typical thermal  
limit temperature), the maximum power dissipation is  
calculated as :  
Thermal resistance consists of two main elements,  
cJC (junction-to-case thermal resistance) and cCA  
(case-to-ambient thermal resistance). cJC is speci-  
fied from the IC junction to the bottom of the thermal  
pad directly below the die. cCA is the resistance from  
the bottom of thermal pad to the ambient air and it  
includes cCS (case-to-sink thermal resistance) and  
cSA (sink-to-ambient thermal resistance). The speci-  
fied path for heat flow is the lowest resistance path  
and it dissipates majority of the heat to the ambient  
air. Typically, cCA is the dominant thermal resistance.  
Therefore, enlarging the internal or bottom ground  
Copyright ANPEC Electronics Corp.  
Rev. A.8 - Oct., 2003  
12  
www.anpec.com.tw