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APL5156BI-TRG 参数 Datasheet PDF下载

APL5156BI-TRG图片预览
型号: APL5156BI-TRG
PDF下载: 下载PDF文件 查看货源
内容描述: 高输入电压,低静态电流器,150mA LDO稳压器 [High Input Voltage, Low Quiescent Current, 150mA LDO Regulator]
分类和应用: 稳压器调节器光电二极管输出元件
文件页数/大小: 18 页 / 303 K
品牌: ANPEC [ ANPEC ELECTRONICS COROPRATION ]
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APL5156  
Application Information  
Enable/Shutdown  
TJ - TA  
PD(MAX)  
=
The APL5156 features an active-high enable pin that al-  
lows the regulator to be disabled. Forcing the enable pin  
low disables the regulator, so current consumed by the  
regulator goes nearly to zero. Forcing the enable pin high  
enables the output voltage. The enable pin can not float.  
qJA  
where TJ-TA is the temperature difference between the  
junction and ambient air. qJA is the thermal resistance  
between junction and ambient air.  
For continual operation, do not exceed the absolute maxi-  
mum junction temperature rating of TJ=125oC.  
For example:  
Input Capacitor  
The APL5156 has high input voltage up to 25V. The input  
capacitor must be rated to sustain voltages that may be  
used on the input. An input capacitor may be required  
when the device is not near the source power supply or  
when supplied by a battery. Small and surface-mounted  
ceramic capacitors can be used for bypassing. A larger  
value may be required if the source supply has high ripple.  
In SOT-23-5 package qJA=235oC/W. When operates the  
APL5156 at TA=50oC, the maximum power dissipation  
can be determined as below:  
PD(MAX)=(125oC-50oC)/(235oC/W)  
PD(MAX)=319.1mW  
Thermal Pad Consideration  
Output Capacitor  
The SOP-8P is a cost-effective package which features a  
small size, like a standard SOP-8, and a bottom thermal  
pad to minimize the thermal resistance of the package is  
applicable to high current applications. The thermal pad  
must be soldered down to the copper plane on circuit  
board. Heat can be conducted away from the thermal  
pad through the copper plane to ambient. If the copper  
plane is not on the top surface of the circuit board, 4 or 6  
vias should be used to thermally couple the thermal pad  
to the bottom plane.  
The APL5156 requires an output capacitor for stability.  
The design requires 2.2mF or greater on the output to  
maintain stability. It is optimized by using low-ESR ce-  
ramic chip capacitors. The maximum allowable ESR is  
3W. More capacitance improves transient response. Place  
the output capacitor as close to the VOUT pin as possible.  
X7R/X5R dielectric-type ceramic capacitors are recom-  
mended because of their temperature performance. X7R  
type capacitors change capacitance by 15% over their  
operating temperature ranges. To use a ceramic chip  
capacitor with Y5V dielectric, the value must be much  
higher than an X7R ceramic capacitor to ensure the same  
minimum capacitance over the equivalent operating tem-  
perature range.  
For good thermal conduction, the vias must be plated  
through and solder filled. The copper plane used to con-  
duct heat away from the thermal pad should be as large  
as practical.  
No-Load Stability  
0.118  
0.072  
The APL5156 will remain stable and in regulation with no  
load unlike many other voltage regulators. This is espe-  
cially important in CMOS RAM keep-alive applications.  
0.024  
0.150  
Thermal Consideration  
The thermal resistance of junction to ambient controls  
the APL5156's maximum power dissipation. The power  
dissipation across the device is PD=IOUT (VIN-VOUT), and the  
maximum power dissipation is:  
ground  
plane for  
thermal  
pad  
0.212  
SOP-8P Layout Recommendation  
Copyright ã ANPEC Electronics Corp.  
9
www.anpec.com.tw  
Rev. A.6 - Oct., 2009