APA0710/0711
Application Descriptions (Cont.)
supply tothe power delivered to the load. Thefollowing
Optimizing Depop Circuitry (Cont.)
equations are the basis for calculating amplifier
efficiency.
size of Cbypass and the turn-on time.
In a SE configuration, the output coupling capacitor,
CC, is of particular concern. This capacitor discharges
through the internal 10kW resistors. Depending on the
size of CC, the time constant can be relatively large.
PO
(7)
Efficiency =
Where :
PSUP
VO,RMS x VO,RMS
RL
VPxVP
2RL
In the most cases, choosing a small value of Ci in the
range of 0.33mF to 1mF, Cbypass being equal to 1mF
shouldproduceavirtuallyclicklessandpoplessturn-on.
PO =
=
VP
Ö2
(8)
VO,RMS =
A high gain amplifier intensifies the problem as the
small delta in voltage is multiplied by the gain. So it is
advantageous to use low-gain configurations.
2VP
pRL
PSUP = VDD x IDD,AVG = VDDx
(9)
Efficiency of a BTL configuration :
Shutdown Function
PO
PSUP
pVP
4VDD
2VP
pRL
VPxVP ) / (VDD x
2RL
) =
(10)
(
=
Inorder to reducepower consumption while not in use,
the APA0710/1 contains a shutdown function to
externally turn off the amplifier bias circuitry. This
shutdown feature turns the amplifier off when a logic
high isplacedon the Shutdown pin forAPA0710 and a
logic low on the Shutdown pin for APA0711.
Po (W)
0.125
0.25
Efficiency (%)
33.6
VP(V)
1.41
PD (W)
0.26
47.6
2.00
0.29
The trigger point between a logic high and logic low
level is typically 0.4VDD. It is best to switch between
groundand the supply voltageVDD toprovide maximum
deviceperformance.
0.375
58.3
2.45*
0.28
*High peak voltages cause the THD to increase.
Table 1. Efficiency Vs Output Power in 3.3V/8W BTL
Systems.
ByswitchingtheShutdown/Shutdownpintohighlevel/
low level, the amplifier enters a low-current state, IDD
forAPA0710/1. APA0710/1are in shutdown mode. On
normal operating, APA0710’sShutdownpinpull tolow
level and APA0711’s Shutdown pin should pull to high
level tokeeping the IC out of the shutdown mode. The
Shutdown/Shutdown pin should be tied to a definite
voltage to avoid unwanted state changes.
Table 1 employs equation10 to calculate efficiencies
for threedifferent output power levelswhen load is8W.
The efficiency of the amplifier is quite low for lower
power levels and rises sharply as power to the load is
increased resulting in a nearly flat internal power
dissipation over the normal operatingrange.Notethat
the internal dissipation at full output power is less than
in the half power range. Calculatingthe efficiency for a
specific system is the key to proper power supply
design. For a mono 900mW audio system with 8W
loads and a 5V supply, the maximum draw on the
BTL Amplifier Efficiency
An easy-to-use equation to calculate efficiency starts
out asbeing equal to the ratio of power from the power
Copyright ã ANPEC Electronics Corp.
Rev. A.5 - Oct., 2005
23
www.anpec.com.tw
ANPEC [ ANPEC ELECTRONICS COROPRATION ]
