AAT3215
150mA CMOS High Performance LDO
Applications Information
ILOAD
IIN
VIN
EN
VOUT
VIN
LDO
Regulator
BYP
GND
IGND
DC INPUT
CIN
CBYP
COUT
RLOAD
CBYP
IRIPPLE
IBYP + noise
GND
LOOP
GND
RTRACE
RTRACE
RTRACE
RTRACE
ILOAD return + noise and ripple
Figure 1: Common LDO Regulator Layout with CBYP Ripple feedback loop
Figure 2 shows the preferred method for the bypass
and output capacitor connections. For low output
noise and highest possible power supply ripple
rejection performance, it is critical to connect the
bypass and output capacitor directly to the LDO reg-
ulator ground pin. This method will eliminate any
load noise or ripple current feedback through the
LDO regulator.
ILOAD
IIN
VIN
VOUT
BYP
VIN
LDO
Regulator
EN
GND
IGND
CBYP
COUT
RLOAD
DC INPUT
GND
CIN
IBYP only
IRIPPLE
RTRACE
RTRACE
RTRACE
RTRACE
ILOAD return + noise and ripple
Figure 2: Recommended LDO Regulator Layout
can be used as an example for good application
layouts.
Evaluation Board Layout
The AAT3215 evaluation layout follows the recom-
mend printed circuit board layout procedures and
Note: Board layout shown is not to scale.
Figure 3: Evaluation board
component side layout
Figure 4: Evaluation board
solder side layout
Figure 5: Evaluation board
top side silk screen layout /
assembly drawing
3215.2002.03.0.91
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