PRODUCT DATASHEET
AAT2860
TM
ChargePump
Backlight/Flash LED Driver and Multiple LDO Lighting Management Unit
A STOP condition, as shown in Figure 2, is when SCL
changes from low to high followed after the STOP condi-
tion setup time (tSU_STO), by the SDA low-to-high transi-
tion. The master does not issue an ACK and releases
both the SCL and SDA line.
signifies the power on reset (POR) value of a register, the
superscript "2" signifies the default value of "1" for a par-
ticular bit of a register, and the superscript "3" signifies
"Don't Care" or "Reserved."
LDO Control Registers, REG0 and REG1
Transferring Data
Configuring and controlling the AAT2860-x’s three LDO
regulators is performed by applying a low-to-high strobe
on the LDO_SEL pin and then programming registers
REG0 and REG1 over the I2C compatible interface. Two
4-bit nibbles in REG0 set the output voltages for LDOA
and LDOB to one of 16 levels. In REG1, the most-signif-
icant nibble programs LDOC’s output voltage while the
least-significant 4-bit nibble controls each LDO’s ON/OFF
status. Upon power-on reset (POR), all three LDO out-
puts are held to 0V or AGND. The programmed LDO
output voltage will only appear after writing a “1” to
each or all REG1[D3:D1] locations. If a high-to-low tran-
sition is applied to the LDO_SEL pin, all three LDO out-
puts are forced to 0V and the register contents are reset
to their POR values. The available LDO output voltages
are shown in Table 2.
Addresses and data are sent with the most significant bit
transmitted first and the least significant bit transmitted
last. After each address or data transmission, the target
device transmits an ACK signal to indicate that it has
received the transmission. The ACK signal is generated
by the target after the master releases the SDA data line
by driving the SDA data line low.
I2C Serial Programming Registers
The AAT2860’s I2C programming registers are listed in
Table 1. There are six registers, two for backlight LED
configuration/control, one for flash/lamp LED configura-
tion/control, and two registers to control the three LDOs.
For the remainder of this document the superscript "1"
D7
LDOA[3]
LDOC[3]
X3
D6
D5
D4
LODA[0]
LODC[0]
WM[4]
WS[4]
F_HI[0]
X3
D3
LDOB[3]
ENLDO_C
WM[3]
WS[3]
D2
LDOB[2]
ENLDO_B
WM[2]
WS[2]
D1
D0
LODB[0]
X3
LDOA[2]
LDOC[2]
MEQS2
LDOA[1]
LDOC[1]
MAIN_ON
SUB_ON
F_HI[1]
X3
LDOB[1]
ENLDO_A
WM[1]
REG0
REG1
REG2
REG3
REG4
REG5
WM[0]
FLOOR[1]
F_HI[3]2
X3
FLOOR[0]
F_HI[2]2
X3
WS[1]
WS[0]
F_TIME[1]
X3
F_TIME[0]
X3
F_LO[1]2
NOFADE_M2
F_LO[0]2
NOFADE_S2
Table 1: AAT2860-x Configuration/Control Register Allocation.
LDOx[4:0]
LDO VOUT [A/B/C] (V)
LDOx[4:0]
LDO VOUT [A/B/C] (V)
00001
0001
0010
0011
0100
0101
0110
0111
1.51
1.6
1.7
1.8
1.9
2.0
2.1
2.2
1000
1001
1010
1011
1100
1101
1110
1111
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
Table 2: LDO[A:C] Output Voltage Control Data
1. Denotes the default (power-on-reset) value.
2. Denotes default value is "1" or ON.
3. Don't Care or Reserved.
w w w . a n a l o g i c t e c h . c o m
2860.2008.05.1.0
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